| Design Name | SRAM1MB |
| Device, Speed (SpeedFile Version) | XC9536XL, -10 (3.0) |
| Date Created | Mon Mar 30 20:20:38 2009 |
| Created By | Timing Report Generator: version K.39 |
| Copyright | Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. |
| Notes and Warnings |
|---|
| Note: This design contains no timing constraints. |
| Note: A default set of constraints using a delay of 0.000ns will be used for analysis. |
| Performance Summary | |
|---|---|
| Min. Clock Period | 9.000 ns. |
| Max. Clock Frequency (fSYSTEM) | 111.111 MHz. |
| Limited by Clock Pulse Width for phi2 | |
| Pad to Pad Delay (tPD) | 15.900 ns. |
| Setup to Clock at the Pad (tSU) | 6.500 ns. |
| Clock Pad to Output Pad Delay (tCO) | 19.400 ns. |
| Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
|---|---|---|---|---|
| TS1000 | 0.0 | 0.0 | 0 | 0 |
| AUTO_TS_F2F | 0.0 | 0.0 | 0 | 0 |
| AUTO_TS_P2P | 0.0 | 19.4 | 87 | 87 |
| AUTO_TS_P2F | 0.0 | 8.3 | 6 | 6 |
| AUTO_TS_F2P | 0.0 | 17.6 | 55 | 55 |
| Path | Requirement (ns) | Delay (ns) | Slack (ns) |
|---|
| Path | Requirement (ns) | Delay (ns) | Slack (ns) |
|---|
| Path | Requirement (ns) | Delay (ns) | Slack (ns) |
|---|---|---|---|
| phi2 to ram1_ce | 0.000 | 19.400 | -19.400 |
| phi2 to casinh_out | 0.000 | 19.000 | -19.000 |
| phi2 to ram1_oe | 0.000 | 19.000 | -19.000 |
| Path | Requirement (ns) | Delay (ns) | Slack (ns) |
|---|---|---|---|
| halt to registered_halt.D | 0.000 | 8.300 | -8.300 |
| mode_select_in<0> to mode_select<0>.D | 0.000 | 8.300 | -8.300 |
| mode_select_in<1> to mode_select<1>.D | 0.000 | 8.300 | -8.300 |
| Path | Requirement (ns) | Delay (ns) | Slack (ns) |
|---|---|---|---|
| mode_select<0>.Q to ram1_ce | 0.000 | 17.600 | -17.600 |
| mode_select<1>.Q to ram1_ce | 0.000 | 17.600 | -17.600 |
| mode_select<2>.Q to ram1_ce | 0.000 | 17.600 | -17.600 |
| Clock | fEXT (MHz) | Reason |
|---|---|---|
| phi2 | 111.111 | Limited by Clock Pulse Width for phi2 |
| Source Pad | Setup to clk (edge) | Hold to clk (edge) |
|---|---|---|
| halt | 6.500 | 0.000 |
| mode_select_in<0> | 6.500 | 0.000 |
| mode_select_in<1> | 6.500 | 0.000 |
| mode_select_in<2> | 6.500 | 0.000 |
| write_protect_in | 6.500 | 0.000 |
| Destination Pad | Clock (edge) to Pad |
|---|---|
| ram1_ce | 19.400 |
| casinh_out | 19.000 |
| ram1_oe | 19.000 |
| ram2_oe | 19.000 |
| ram_we | 19.000 |
| rd_led | 19.000 |
| wr_led | 19.000 |
| basic | 18.000 |
| map_selftest | 18.000 |
| ram2_ce | 18.000 |
| ram_a<14> | 18.000 |
| ram_a<15> | 18.000 |
| ram_a<16> | 18.000 |
| ram_a<17> | 18.000 |
| ram_a<18> | 18.000 |
| Source Pad | Destination Pad | Delay |
|---|---|---|
| portb<1> | ram1_ce | 15.900 |
| portb<5> | ram1_ce | 15.900 |
| a<14> | ram1_oe | 15.500 |
| a<14> | ram2_oe | 15.500 |
| a<14> | ram_we | 15.500 |
| a<14> | rd_led | 15.500 |
| a<14> | wr_led | 15.500 |
| a<15> | ram1_oe | 15.500 |
| a<15> | ram2_oe | 15.500 |
| a<15> | ram_we | 15.500 |
| a<15> | rd_led | 15.500 |
| a<15> | wr_led | 15.500 |
| casinh_in | casinh_out | 15.500 |
| casinh_in | ram1_oe | 15.500 |
| casinh_in | ram2_oe | 15.500 |
| casinh_in | ram_we | 15.500 |
| casinh_in | rd_led | 15.500 |
| casinh_in | wr_led | 15.500 |
| phi0 | ram1_ce | 15.500 |
| phi0 | ram_we | 15.500 |
| phi2 | ram1_oe | 15.500 |
| phi2 | ram2_oe | 15.500 |
| phi2 | ram_we | 15.500 |
| portb<4> | ram1_ce | 15.500 |
| portb<5> | casinh_out | 15.500 |
| portb<5> | ram1_oe | 15.500 |
| portb<5> | ram2_oe | 15.500 |
| portb<5> | ram_we | 15.500 |
| portb<5> | rd_led | 15.500 |
| portb<5> | wr_led | 15.500 |
| rw | ram1_ce | 15.500 |
| rw | ram1_oe | 15.500 |
| rw | ram2_oe | 15.500 |
| rw | ram_we | 15.500 |
| rw | rd_led | 15.500 |
| rw | wr_led | 15.500 |
| a<14> | casinh_out | 14.500 |
| a<14> | ram1_ce | 14.500 |
| a<14> | ram2_ce | 14.500 |
| a<15> | casinh_out | 14.500 |
| a<15> | ram1_ce | 14.500 |
| a<15> | ram2_ce | 14.500 |
| casinh_in | ram1_ce | 14.500 |
| casinh_in | ram2_ce | 14.500 |
| phi0 | ram2_ce | 14.500 |
| phi2 | ram1_ce | 14.500 |
| phi2 | ram2_ce | 14.500 |
| portb<1> | basic | 14.500 |
| portb<1> | ram2_ce | 14.500 |
| portb<1> | ram_a<14> | 14.500 |
| portb<2> | ram_a<14> | 14.500 |
| portb<2> | ram_a<15> | 14.500 |
| portb<3> | ram_a<15> | 14.500 |
| portb<3> | ram_a<16> | 14.500 |
| portb<4> | basic | 14.500 |
| portb<4> | casinh_out | 14.500 |
| portb<4> | map_selftest | 14.500 |
| portb<4> | ram1_oe | 14.500 |
| portb<4> | ram2_ce | 14.500 |
| portb<4> | ram2_oe | 14.500 |
| portb<4> | ram_we | 14.500 |
| portb<4> | rd_led | 14.500 |
| portb<4> | wr_led | 14.500 |
| portb<5> | basic | 14.500 |
| portb<5> | map_selftest | 14.500 |
| portb<5> | ram_a<16> | 14.500 |
| portb<6> | ram_a<16> | 14.500 |
| portb<6> | ram_a<17> | 14.500 |
| portb<7> | map_selftest | 14.500 |
| portb<7> | ram_a<17> | 14.500 |
| portb<7> | ram_a<18> | 14.500 |
| rw | ram2_ce | 14.500 |