| ********** Mapped Logic ********** |
|
basic <= ((portb(1))
OR (NOT portb(4) AND mode_select(2) AND mode_select(1)) OR (NOT portb(5) AND mode_select(2) AND mode_select(1) AND NOT mode_select(0))); |
|
casinh_out <= ((EXP6_.EXP)
OR (EXP7_.EXP) OR (casinh_in AND NOT a(14)) OR (casinh_in AND a(15)) OR (portb(4) AND registered_halt AND casinh_in) OR (portb(4) AND mode_select(2) AND mode_select(0) AND casinh_in) OR (portb(4) AND mode_select(1) AND mode_select(0) AND casinh_in)); |
|
map_selftest <= ((portb(7))
OR (NOT portb(4) AND mode_select(2)) OR (NOT portb(5) AND mode_select(2) AND NOT mode_select(0))); |
| FDCPE_mode_select0: FDCPE port map (mode_select(0),mode_select_in(0),NOT phi2,'0','0'); |
| FDCPE_mode_select1: FDCPE port map (mode_select(1),mode_select_in(1),NOT phi2,'0','0'); |
| FDCPE_mode_select2: FDCPE port map (mode_select(2),mode_select_in(2),NOT phi2,'0','0'); |
|
ram1_ce <= ((NOT phi2)
OR (NOT casinh_in) OR (NOT a(14)) OR (a(15)) OR (EXP9_.EXP) OR (portb(4) AND registered_halt)); |
|
ram1_oe <= NOT (((ram2_ce_OBUF.EXP)
OR (rw AND phi2 AND NOT portb(4) AND mode_select(2) AND mode_select(0) AND casinh_in AND a(14) AND NOT a(15)) OR (rw AND phi2 AND NOT portb(4) AND mode_select(2) AND registered_halt AND casinh_in AND a(14) AND NOT a(15)) OR (rw AND phi2 AND NOT portb(4) AND mode_select(1) AND mode_select(0) AND casinh_in AND a(14) AND NOT a(15)) OR (rw AND phi2 AND NOT portb(4) AND mode_select(1) AND registered_halt AND casinh_in AND a(14) AND NOT a(15)) OR (rw AND phi2 AND NOT portb(4) AND mode_select(0) AND registered_halt AND casinh_in AND a(14) AND NOT a(15)))); |
|
ram2_ce <= NOT (((rw AND phi2 AND NOT portb(4) AND mode_select(2) AND
mode_select(1) AND mode_select(0) AND casinh_in AND a(14) AND NOT a(15) AND NOT portb(1)) OR (phi2 AND NOT portb(4) AND mode_select(2) AND mode_select(1) AND mode_select(0) AND write_protect AND casinh_in AND a(14) AND NOT a(15) AND phi0 AND NOT portb(1)))); |
|
ram2_oe <= NOT (((EXP10_.EXP)
OR (rw AND phi2 AND NOT portb(4) AND mode_select(2) AND mode_select(0) AND casinh_in AND a(14) AND NOT a(15)) OR (rw AND phi2 AND NOT portb(4) AND mode_select(2) AND registered_halt AND casinh_in AND a(14) AND NOT a(15)) OR (rw AND phi2 AND NOT portb(4) AND mode_select(1) AND mode_select(0) AND casinh_in AND a(14) AND NOT a(15)) OR (rw AND phi2 AND NOT portb(4) AND mode_select(1) AND registered_halt AND casinh_in AND a(14) AND NOT a(15)) OR (rw AND phi2 AND NOT portb(4) AND mode_select(0) AND registered_halt AND casinh_in AND a(14) AND NOT a(15)))); |
|
ram_a(14) <= ((mode_select(0) AND portb(2))
OR (mode_select(2) AND NOT mode_select(1) AND portb(2)) OR (NOT mode_select(2) AND mode_select(1) AND portb(2)) OR (mode_select(2) AND mode_select(1) AND NOT mode_select(0) AND portb(1))); |
|
ram_a(15) <= ((mode_select(0) AND portb(3))
OR (mode_select(2) AND NOT mode_select(1) AND portb(3)) OR (NOT mode_select(2) AND mode_select(1) AND portb(3)) OR (mode_select(2) AND mode_select(1) AND NOT mode_select(0) AND portb(2))); |
|
ram_a(16) <= ((portb(5) AND mode_select(2) AND mode_select(0))
OR (portb(5) AND mode_select(1) AND mode_select(0)) OR (mode_select(2) AND mode_select(1) AND NOT mode_select(0) AND portb(3)) OR (mode_select(2) AND NOT mode_select(1) AND NOT mode_select(0) AND portb(6)) OR (NOT mode_select(2) AND mode_select(1) AND NOT mode_select(0) AND portb(6))); |
|
ram_a(17) <= ((mode_select(2) AND mode_select(1) AND portb(6))
OR (mode_select(2) AND mode_select(0) AND portb(6)) OR (mode_select(1) AND mode_select(0) AND portb(6)) OR (portb(7) AND mode_select(2) AND NOT mode_select(1) AND NOT mode_select(0))); |
|
ram_a(18) <= ((portb(7) AND mode_select(2) AND mode_select(1))
OR (portb(7) AND mode_select(2) AND mode_select(0))); |
|
ram_we <= NOT (((map_selftest_OBUF.EXP)
OR (registered_halt.EXP) OR (NOT rw AND phi2 AND NOT portb(4) AND mode_select(2) AND mode_select(0) AND write_protect AND casinh_in AND a(14) AND NOT a(15) AND phi0) OR (NOT rw AND phi2 AND NOT portb(4) AND mode_select(2) AND registered_halt AND write_protect AND casinh_in AND a(14) AND NOT a(15) AND phi0) OR (NOT rw AND phi2 AND NOT portb(4) AND mode_select(1) AND mode_select(0) AND write_protect AND casinh_in AND a(14) AND NOT a(15) AND phi0) OR (NOT rw AND phi2 AND NOT portb(4) AND mode_select(1) AND registered_halt AND write_protect AND casinh_in AND a(14) AND NOT a(15) AND phi0) OR (NOT rw AND phi2 AND NOT portb(4) AND mode_select(0) AND registered_halt AND write_protect AND casinh_in AND a(14) AND NOT a(15) AND phi0))); |
|
rd_led <= NOT (((EXP4_.EXP)
OR (EXP5_.EXP) OR (rw AND NOT portb(4) AND mode_select(2) AND mode_select(0) AND casinh_in AND a(14) AND NOT a(15)) OR (rw AND NOT portb(4) AND mode_select(2) AND registered_halt AND casinh_in AND a(14) AND NOT a(15)) OR (rw AND NOT portb(4) AND mode_select(1) AND mode_select(0) AND casinh_in AND a(14) AND NOT a(15)) OR (rw AND NOT portb(4) AND mode_select(1) AND registered_halt AND casinh_in AND a(14) AND NOT a(15)) OR (rw AND NOT portb(4) AND mode_select(0) AND registered_halt AND casinh_in AND a(14) AND NOT a(15)))); |
| FDCPE_registered_halt: FDCPE port map (registered_halt,halt,NOT phi2,'0','0'); |
|
wr_led <= NOT (((ram_hi_address(18).EXP)
OR (ram_hi_address(17).EXP) OR (NOT rw AND NOT portb(4) AND mode_select(2) AND mode_select(0) AND write_protect AND casinh_in AND a(14) AND NOT a(15)) OR (NOT rw AND NOT portb(4) AND mode_select(2) AND registered_halt AND write_protect AND casinh_in AND a(14) AND NOT a(15)) OR (NOT rw AND NOT portb(4) AND mode_select(1) AND mode_select(0) AND write_protect AND casinh_in AND a(14) AND NOT a(15)) OR (NOT rw AND NOT portb(4) AND mode_select(1) AND registered_halt AND write_protect AND casinh_in AND a(14) AND NOT a(15)) OR (NOT rw AND NOT portb(4) AND mode_select(0) AND registered_halt AND write_protect AND casinh_in AND a(14) AND NOT a(15)))); |
| FDCPE_write_protect: FDCPE port map (write_protect,write_protect_in,NOT phi2,'0','0'); |
|
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |