cpldfit:  version K.39                              Xilinx Inc.
                                  Fitter Report
Design Name: SRAM1MB                             Date:  3-30-2009,  8:20PM
Device Used: XC9536XL-10-PC44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
20 /36  ( 56%) 93  /180  ( 52%) 39 /108 ( 36%)   5  /36  ( 14%) 33 /34  ( 97%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1          11/18       22/54       41/90      16/17
FB2           9/18       17/54       52/90      17/17*
             -----       -----       -----      -----    
             20/36       39/108      93/180     33/34 

* - Resource is exhausted

** Global Control Resources **

Signal 'phi2' mapped onto global clock net GCK2.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :   17          17    |  I/O              :    28      28
Output        :   15          15    |  GCK/IO           :     2       3
Bidirectional :    0           0    |  GTS/IO           :     2       2
GCK           :    1           1    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     33          33

** Power Data **

There are 20 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 15 Outputs **

Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                Pts   Inps          No.  Type    Use     Mode Rate State
ram_a<15>           4     5     FB1_1   2    I/O     O       STD  SLOW 
ram_a<16>           5     6     FB1_2   3    I/O     O       STD  SLOW 
rd_led              8     10    FB1_4   4    I/O     O       STD  SLOW 
casinh_out          8     9     FB1_10  12   I/O     O       STD  SLOW 
map_selftest        3     5     FB1_13  18   I/O     O       STD  SLOW 
ram_we              8     13    FB1_14  19   I/O     O       STD  SLOW 
ram_a<14>           4     5     FB2_1   1    I/O     O       STD  SLOW 
ram_a<18>           2     4     FB2_2   44   I/O     O       STD  SLOW 
wr_led              8     11    FB2_3   42   GTS/I/O O       STD  SLOW 
ram_a<17>           4     5     FB2_4   43   I/O     O       STD  SLOW 
basic               3     6     FB2_5   40   GTS/I/O O       STD  SLOW 
ram1_ce             13    14    FB2_14  28   I/O     O       STD  SLOW 
ram1_oe             8     11    FB2_15  27   I/O     O       STD  SLOW 
ram2_ce             2     12    FB2_16  26   I/O     O       STD  SLOW 
ram2_oe             8     11    FB2_17  25   I/O     O       STD  SLOW 

** 5 Buried Nodes **

Signal              Total Total Loc     Pwr  Reg Init
Name                Pts   Inps          Mode State
write_protect       1     1     FB1_12  STD  RESET
registered_halt     1     1     FB1_15  STD  RESET
mode_select<2>      1     1     FB1_16  STD  RESET
mode_select<1>      1     1     FB1_17  STD  RESET
mode_select<0>      1     1     FB1_18  STD  RESET

** 18 Inputs **

Signal              Loc     Pin  Pin     Pin     
Name                        No.  Type    Use     
phi0                FB1_3   5    GCK/I/O I
phi2                FB1_5   6    GCK/I/O GCK/I
a<14>               FB1_6   8    I/O     I
a<15>               FB1_8   9    I/O     I
casinh_in           FB1_9   11   I/O     I
halt                FB1_11  13   I/O     I
rw                  FB1_12  14   I/O     I
mode_select_in<2>   FB1_15  20   I/O     I
mode_select_in<1>   FB1_16  22   I/O     I
mode_select_in<0>   FB1_17  24   I/O     I
write_protect_in    FB2_6   39   GSR/I/O I
portb<7>            FB2_7   38   I/O     I
portb<6>            FB2_8   37   I/O     I
portb<5>            FB2_9   36   I/O     I
portb<4>            FB2_10  35   I/O     I
portb<3>            FB2_11  34   I/O     I
portb<2>            FB2_12  33   I/O     I
portb<1>            FB2_13  29   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               22/32
Number of signals used by logic mapping into function block:  22
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
ram_a<15>             4       0     0   1     FB1_1   2     I/O     O
ram_a<16>             5       0     0   0     FB1_2   3     I/O     O
(unused)              0       0   \/2   3     FB1_3   5     GCK/I/O I
rd_led                8       3<-   0   0     FB1_4   4     I/O     O
(unused)              0       0   /\1   4     FB1_5   6     GCK/I/O GCK/I
(unused)              0       0     0   5     FB1_6   8     I/O     I
(unused)              0       0     0   5     FB1_7   7     GCK/I/O 
(unused)              0       0     0   5     FB1_8   9     I/O     I
(unused)              0       0   \/2   3     FB1_9   11    I/O     I
casinh_out            8       3<-   0   0     FB1_10  12    I/O     O
(unused)              0       0   /\1   4     FB1_11  13    I/O     I
write_protect         1       0     0   4     FB1_12  14    I/O     I
map_selftest          3       0   \/1   1     FB1_13  18    I/O     O
ram_we                8       3<-   0   0     FB1_14  19    I/O     O
registered_halt       1       0   /\2   2     FB1_15  20    I/O     I
mode_select<2>        1       0     0   4     FB1_16  22    I/O     I
mode_select<1>        1       0     0   4     FB1_17  24    I/O     I
mode_select<0>        1       0     0   4     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: a<14>               9: mode_select_in<1>  16: portb<5> 
  2: a<15>              10: mode_select_in<2>  17: portb<6> 
  3: casinh_in          11: phi0               18: portb<7> 
  4: halt               12: phi2               19: registered_halt 
  5: mode_select<0>     13: portb<2>           20: rw 
  6: mode_select<1>     14: portb<3>           21: write_protect 
  7: mode_select<2>     15: portb<4>           22: write_protect_in 
  8: mode_select_in<0> 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
ram_a<15>            ....XXX.....XX.......................... 5
ram_a<16>            ....XXX......X.XX....................... 6
rd_led               XXX.XXX.......XX..XX.................... 10
casinh_out           XXX.XXX.......XX..X..................... 9
write_protect        .....................X.................. 1
map_selftest         ....X.X.......XX.X...................... 5
ram_we               XXX.XXX...XX..XX..XXX................... 13
registered_halt      ...X.................................... 1
mode_select<2>       .........X.............................. 1
mode_select<1>       ........X............................... 1
mode_select<0>       .......X................................ 1
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               17/37
Number of signals used by logic mapping into function block:  17
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
ram_a<14>             4       0     0   1     FB2_1   1     I/O     O
ram_a<18>             2       0   \/2   1     FB2_2   44    I/O     O
wr_led                8       3<-   0   0     FB2_3   42    GTS/I/O O
ram_a<17>             4       0   /\1   0     FB2_4   43    I/O     O
basic                 3       0     0   2     FB2_5   40    GTS/I/O O
(unused)              0       0     0   5     FB2_6   39    GSR/I/O I
(unused)              0       0     0   5     FB2_7   38    I/O     I
(unused)              0       0     0   5     FB2_8   37    I/O     I
(unused)              0       0     0   5     FB2_9   36    I/O     I
(unused)              0       0     0   5     FB2_10  35    I/O     I
(unused)              0       0     0   5     FB2_11  34    I/O     I
(unused)              0       0   \/3   2     FB2_12  33    I/O     I
(unused)              0       0   \/5   0     FB2_13  29    I/O     I
ram1_ce              13       8<-   0   0     FB2_14  28    I/O     O
ram1_oe               8       3<-   0   0     FB2_15  27    I/O     O
ram2_ce               2       0   /\3   0     FB2_16  26    I/O     O
ram2_oe               8       3<-   0   0     FB2_17  25    I/O     O
(unused)              0       0   /\3   2     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: a<14>              7: phi0              13: portb<6> 
  2: a<15>              8: phi2              14: portb<7> 
  3: casinh_in          9: portb<1>          15: registered_halt 
  4: mode_select<0>    10: portb<2>          16: rw 
  5: mode_select<1>    11: portb<4>          17: write_protect 
  6: mode_select<2>    12: portb<5>         

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
ram_a<14>            ...XXX..XX.............................. 5
ram_a<18>            ...XXX.......X.......................... 4
wr_led               XXXXXX....XX..XXX....................... 11
ram_a<17>            ...XXX......XX.......................... 5
basic                ...XXX..X.XX............................ 6
ram1_ce              XXXXXXXXX.XX..XXX....................... 14
ram1_oe              XXXXXX.X..XX..XX........................ 11
ram2_ce              XXXXXXXXX.X....XX....................... 12
ram2_oe              XXXXXX.X..XX..XX........................ 11
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********
















basic <= ((portb(1))
	OR (NOT portb(4) AND mode_select(2) AND mode_select(1))
	OR (NOT portb(5) AND mode_select(2) AND mode_select(1) AND 
	NOT mode_select(0)));


casinh_out <= ((EXP6_.EXP)
	OR (EXP7_.EXP)
	OR (casinh_in AND NOT a(14))
	OR (casinh_in AND a(15))
	OR (portb(4) AND registered_halt AND casinh_in)
	OR (portb(4) AND mode_select(2) AND mode_select(0) AND 
	casinh_in)
	OR (portb(4) AND mode_select(1) AND mode_select(0) AND 
	casinh_in));


map_selftest <= ((portb(7))
	OR (NOT portb(4) AND mode_select(2))
	OR (NOT portb(5) AND mode_select(2) AND NOT mode_select(0)));

FDCPE_mode_select0: FDCPE port map (mode_select(0),mode_select_in(0),NOT phi2,'0','0');

FDCPE_mode_select1: FDCPE port map (mode_select(1),mode_select_in(1),NOT phi2,'0','0');

FDCPE_mode_select2: FDCPE port map (mode_select(2),mode_select_in(2),NOT phi2,'0','0');


ram1_ce <= ((NOT phi2)
	OR (NOT casinh_in)
	OR (NOT a(14))
	OR (a(15))
	OR (EXP9_.EXP)
	OR (portb(4) AND registered_halt));


ram1_oe <= NOT (((ram2_ce_OBUF.EXP)
	OR (rw AND phi2 AND NOT portb(4) AND mode_select(2) AND 
	mode_select(0) AND casinh_in AND a(14) AND NOT a(15))
	OR (rw AND phi2 AND NOT portb(4) AND mode_select(2) AND 
	registered_halt AND casinh_in AND a(14) AND NOT a(15))
	OR (rw AND phi2 AND NOT portb(4) AND mode_select(1) AND 
	mode_select(0) AND casinh_in AND a(14) AND NOT a(15))
	OR (rw AND phi2 AND NOT portb(4) AND mode_select(1) AND 
	registered_halt AND casinh_in AND a(14) AND NOT a(15))
	OR (rw AND phi2 AND NOT portb(4) AND mode_select(0) AND 
	registered_halt AND casinh_in AND a(14) AND NOT a(15))));


ram2_ce <= NOT (((rw AND phi2 AND NOT portb(4) AND mode_select(2) AND 
	mode_select(1) AND mode_select(0) AND casinh_in AND a(14) AND NOT a(15) AND 
	NOT portb(1))
	OR (phi2 AND NOT portb(4) AND mode_select(2) AND 
	mode_select(1) AND mode_select(0) AND write_protect AND casinh_in AND 
	a(14) AND NOT a(15) AND phi0 AND NOT portb(1))));


ram2_oe <= NOT (((EXP10_.EXP)
	OR (rw AND phi2 AND NOT portb(4) AND mode_select(2) AND 
	mode_select(0) AND casinh_in AND a(14) AND NOT a(15))
	OR (rw AND phi2 AND NOT portb(4) AND mode_select(2) AND 
	registered_halt AND casinh_in AND a(14) AND NOT a(15))
	OR (rw AND phi2 AND NOT portb(4) AND mode_select(1) AND 
	mode_select(0) AND casinh_in AND a(14) AND NOT a(15))
	OR (rw AND phi2 AND NOT portb(4) AND mode_select(1) AND 
	registered_halt AND casinh_in AND a(14) AND NOT a(15))
	OR (rw AND phi2 AND NOT portb(4) AND mode_select(0) AND 
	registered_halt AND casinh_in AND a(14) AND NOT a(15))));


ram_a(14) <= ((mode_select(0) AND portb(2))
	OR (mode_select(2) AND NOT mode_select(1) AND portb(2))
	OR (NOT mode_select(2) AND mode_select(1) AND portb(2))
	OR (mode_select(2) AND mode_select(1) AND NOT mode_select(0) AND 
	portb(1)));


ram_a(15) <= ((mode_select(0) AND portb(3))
	OR (mode_select(2) AND NOT mode_select(1) AND portb(3))
	OR (NOT mode_select(2) AND mode_select(1) AND portb(3))
	OR (mode_select(2) AND mode_select(1) AND NOT mode_select(0) AND 
	portb(2)));


ram_a(16) <= ((portb(5) AND mode_select(2) AND mode_select(0))
	OR (portb(5) AND mode_select(1) AND mode_select(0))
	OR (mode_select(2) AND mode_select(1) AND NOT mode_select(0) AND 
	portb(3))
	OR (mode_select(2) AND NOT mode_select(1) AND NOT mode_select(0) AND 
	portb(6))
	OR (NOT mode_select(2) AND mode_select(1) AND NOT mode_select(0) AND 
	portb(6)));


ram_a(17) <= ((mode_select(2) AND mode_select(1) AND portb(6))
	OR (mode_select(2) AND mode_select(0) AND portb(6))
	OR (mode_select(1) AND mode_select(0) AND portb(6))
	OR (portb(7) AND mode_select(2) AND NOT mode_select(1) AND 
	NOT mode_select(0)));


ram_a(18) <= ((portb(7) AND mode_select(2) AND mode_select(1))
	OR (portb(7) AND mode_select(2) AND mode_select(0)));


ram_we <= NOT (((map_selftest_OBUF.EXP)
	OR (registered_halt.EXP)
	OR (NOT rw AND phi2 AND NOT portb(4) AND mode_select(2) AND 
	mode_select(0) AND write_protect AND casinh_in AND a(14) AND NOT a(15) AND 
	phi0)
	OR (NOT rw AND phi2 AND NOT portb(4) AND mode_select(2) AND 
	registered_halt AND write_protect AND casinh_in AND a(14) AND NOT a(15) AND 
	phi0)
	OR (NOT rw AND phi2 AND NOT portb(4) AND mode_select(1) AND 
	mode_select(0) AND write_protect AND casinh_in AND a(14) AND NOT a(15) AND 
	phi0)
	OR (NOT rw AND phi2 AND NOT portb(4) AND mode_select(1) AND 
	registered_halt AND write_protect AND casinh_in AND a(14) AND NOT a(15) AND 
	phi0)
	OR (NOT rw AND phi2 AND NOT portb(4) AND mode_select(0) AND 
	registered_halt AND write_protect AND casinh_in AND a(14) AND NOT a(15) AND 
	phi0)));


rd_led <= NOT (((EXP4_.EXP)
	OR (EXP5_.EXP)
	OR (rw AND NOT portb(4) AND mode_select(2) AND mode_select(0) AND 
	casinh_in AND a(14) AND NOT a(15))
	OR (rw AND NOT portb(4) AND mode_select(2) AND 
	registered_halt AND casinh_in AND a(14) AND NOT a(15))
	OR (rw AND NOT portb(4) AND mode_select(1) AND mode_select(0) AND 
	casinh_in AND a(14) AND NOT a(15))
	OR (rw AND NOT portb(4) AND mode_select(1) AND 
	registered_halt AND casinh_in AND a(14) AND NOT a(15))
	OR (rw AND NOT portb(4) AND mode_select(0) AND 
	registered_halt AND casinh_in AND a(14) AND NOT a(15))));

FDCPE_registered_halt: FDCPE port map (registered_halt,halt,NOT phi2,'0','0');


wr_led <= NOT (((ram_hi_address(18).EXP)
	OR (ram_hi_address(17).EXP)
	OR (NOT rw AND NOT portb(4) AND mode_select(2) AND mode_select(0) AND 
	write_protect AND casinh_in AND a(14) AND NOT a(15))
	OR (NOT rw AND NOT portb(4) AND mode_select(2) AND 
	registered_halt AND write_protect AND casinh_in AND a(14) AND NOT a(15))
	OR (NOT rw AND NOT portb(4) AND mode_select(1) AND mode_select(0) AND 
	write_protect AND casinh_in AND a(14) AND NOT a(15))
	OR (NOT rw AND NOT portb(4) AND mode_select(1) AND 
	registered_halt AND write_protect AND casinh_in AND a(14) AND NOT a(15))
	OR (NOT rw AND NOT portb(4) AND mode_select(0) AND 
	registered_halt AND write_protect AND casinh_in AND a(14) AND NOT a(15))));

FDCPE_write_protect: FDCPE port map (write_protect,write_protect_in,NOT phi2,'0','0');

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9536XL-10-PC44


   --------------------------------  
  /6  5  4  3  2  1  44 43 42 41 40 \
 | 7                             39 | 
 | 8                             38 | 
 | 9                             37 | 
 | 10                            36 | 
 | 11       XC9536XL-10-PC44     35 | 
 | 12                            34 | 
 | 13                            33 | 
 | 14                            32 | 
 | 15                            31 | 
 | 16                            30 | 
 | 17                            29 | 
 \ 18 19 20 21 22 23 24 25 26 27 28 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 ram_a<14>                        23 GND                           
  2 ram_a<15>                        24 mode_select_in<0>             
  3 ram_a<16>                        25 ram2_oe                       
  4 rd_led                           26 ram2_ce                       
  5 phi0                             27 ram1_oe                       
  6 phi2                             28 ram1_ce                       
  7 KPR                              29 portb<1>                      
  8 a<14>                            30 TDO                           
  9 a<15>                            31 GND                           
 10 GND                              32 VCC                           
 11 casinh_in                        33 portb<2>                      
 12 casinh_out                       34 portb<3>                      
 13 halt                             35 portb<4>                      
 14 rw                               36 portb<5>                      
 15 TDI                              37 portb<6>                      
 16 TMS                              38 portb<7>                      
 17 TCK                              39 write_protect_in              
 18 map_selftest                     40 basic                         
 19 ram_we                           41 VCC                           
 20 mode_select_in<2>                42 wr_led                        
 21 VCC                              43 ram_a<17>                     
 22 mode_select_in<1>                44 ram_a<18>                     


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9536xl-10-PC44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25